Contains all classes and functions related to Fletchgen. More...

Namespaces
	meta
	Fletchgen metadata keys for Cerata objects.

Classes
struct	Axi4LiteSpec
	AXI4-lite bus specification. More...

struct	Axi4LitePort
	An AXI4-lite port derived from an AXI4-lite specification. More...

struct	BusDim
	Holds bus interface dimensions. More...

struct	BusDimParams
	Holds bus parameters based on bus dimensions, that has actual nodes representing the dimensions. More...

struct	BusSpecParams
	Holds bus parameters and function based on bus dimensions, that has actual nodes representing the dimensions. More...

struct	BusSpec
	Holds bus dimensions and function, without instantiating Cerata nodes. More...

struct	BusPort
	A port derived from bus parameters. More...

struct	Design
	A structure for all components in a Fletcher design. More...

struct	Kernel
	The Kernel component to be implemented by the user. More...

class	Mantle
	A component that wraps a Kernel and all ArrayReaders/Writers resulting from a Schema set. More...

struct	MmioReg
	Structure to represent an MMIO register. More...

struct	MmioPort
	A port on the vhdmmio component. Remembers what register spec it came from. More...

struct	Nucleus
	It's like a kernel, but there is a kernel inside. More...

struct	Options
	Fletcher program options. More...

struct	FieldPort
	A port derived from an Arrow field. More...

struct	RecordBatch
	A RecordBatch aggregating ArrayReaders/Writers. More...

class	FletcherSchema

class	SchemaSet
	A named set of schemas. More...

Typedefs
using	RBVector = std::vector< std::shared_ptr< arrow::RecordBatch > >
	Short-hand for vector of RecordBatches.

using	NodeProfilerPorts = std::map< Node , std::pair< std::vector< Instance >, std::vector< Port * > >>
	A mapping from nodes to profiler instances and ports.

using	Status = putong::Status< Error >

Enumerations
enum class	ConfigType { ARB , NUL , PRIM , LIST , LIST_PRIM , STRUCT }
	Types for ArrayReader/Writer configuration string. More...

enum class	BusFunction { READ , WRITE }
	Defines function of a bus interface (read/write). More...

enum class	MmioFunction { DEFAULT , BATCH , BUFFER , KERNEL , PROFILE }
	Register intended use enumeration. More...

enum class	MmioBehavior { CONTROL , STATUS , STROBE }
	Register access behavior enumeration. More...

enum class	Error { GenericError , YAMLError }
	Error types.

Functions
size_t	GetCtrlBufferCount (const arrow::Field &field)
	Return the number of buffers for the control field.

uint32_t	GetTagWidth (const arrow::Field &field)
	Return the tag width of this field as a literal node. Settable through Arrow metadata. Default: 1.

std::shared_ptr< Type >	cmd_type (const std::shared_ptr< Node > &index_width, const std::shared_ptr< Node > &tag_width, const std::optional< std::shared_ptr< Node >> &ctrl_width=std::nullopt)
	Return a Fletcher command stream type.

std::shared_ptr< Type >	unlock_type (const std::shared_ptr< Node > &tag_width)
	Fletcher unlock stream.

std::shared_ptr< Type >	array_reader_out (uint32_t num_streams=0, uint32_t full_width=0)
	Fletcher read data.

std::shared_ptr< Type >	array_writer_in (uint32_t num_streams=0, uint32_t full_width=0)
	Fletcher write data.

std::shared_ptr< Type >	array_reader_out (std::pair< uint32_t, uint32_t > spec)
	Fletcher read data, where the pair contains {num_streams, full_width}.

std::shared_ptr< Type >	array_writer_in (std::pair< uint32_t, uint32_t > spec)
	Fletcher write data, where the pair contains {num_streams, full_width}.

Component *	array (Mode mode)
	Return a Cerata component model of an Array(Reader/Writer). More...

ConfigType	GetConfigType (const arrow::DataType &type)
	Return the configuration string type version of an arrow::DataType. More...

std::shared_ptr< Node >	GetWidthNode (const arrow::DataType &type)
	Return a node representing the width of a (flat) Arrow DataType. More...

std::string	GenerateConfigString (const arrow::Field &field, int level=0)
	Return the configuration string for a ArrayReader/Writer. More...

std::shared_ptr< TypeMapper >	GetStreamTypeMapper (Type stream_type, Type other)
	Get a type mapper for an Arrow::Field-based stream to an ArrayReader/Writer stream. More...

std::shared_ptr< Type >	ListPrimType (int val_epc, int list_epc, int val_width, int idx_width, const std::string &name)

std::shared_ptr< Type >	GetStreamType (const arrow::Field &arrow_field, fletcher::Mode mode, int level=0)
	Convert an Arrow::Field into a stream type. More...

std::pair< uint32_t, uint32_t >	GetArrayDataSpec (const arrow::Field &arrow_field)
	Get the ArrayR/W number of streams and data width from an Arrow Field. More...

Component *	array (fletcher::Mode mode)
	Return a Cerata component model of an ArrayReader/Writers. More...

std::shared_ptr< Type >	axi4_lite_type (Axi4LiteSpec spec=Axi4LiteSpec())
	AXI4-lite port type.

std::shared_ptr< Axi4LitePort >	axi4_lite (Port::Dir dir, const std::shared_ptr< ClockDomain > &domain=cerata::default_domain(), Axi4LiteSpec spec=Axi4LiteSpec())
	Make a new AXI4-lite port, returning a shared pointer to it. More...

std::shared_ptr< ClockDomain >	kernel_cd ()
	Fletcher accelerator clock domain.

std::shared_ptr< ClockDomain >	bus_cd ()
	Fletcher bus clock domain.

std::shared_ptr< Type >	cr ()
	Fletcher clock/reset;.

std::shared_ptr< Type >	valid (int width=1, bool on_primitive=false)
	Fletcher valid.

std::shared_ptr< Type >	ready (int width=1, bool on_primitive=false)
	Fletcher ready.

std::shared_ptr< Type >	data (int width)
	Fletcher data.

std::shared_ptr< Type >	length (int width)
	Fletcher length.

std::shared_ptr< Type >	count (int width)
	Fletcher count.

std::shared_ptr< Type >	dvalid (int width=1, bool on_primitive=false)
	Fletcher dvalid.

std::shared_ptr< Type >	last (int width=1, bool on_primitive=false)
	Fletcher last.

int	GetFixedWidthTypeBitWidth (const arrow::DataType &arrow_type)
	Returns the bit-width of a fixed-width Arrow type. Throws if it's not a fixed-width type. More...

std::shared_ptr< Type >	ConvertFixedWidthType (const std::shared_ptr< arrow::DataType > &arrow_type, int epc=1)
	Convert a fixed-width arrow::DataType to a fixed-width Fletcher Type. More...

std::optional< cerata::Port * >	GetClockResetPort (cerata::Graph *graph, const ClockDomain &domain)
	Return the clock/reset port of a graph for a specific clock domain, if it exists. More...

std::shared_ptr< Type >	bus_read (const std::shared_ptr< Node > &addr_width, const std::shared_ptr< Node > &data_width, const std::shared_ptr< Node > &len_width)
	Return a Cerata type for a Fletcher bus read interface.

std::shared_ptr< Type >	bus_write (const std::shared_ptr< Node > &addr_width, const std::shared_ptr< Node > &data_width, const std::shared_ptr< Node > &len_width)
	Return a Cerata type for a Fletcher bus write interface.

Component *	bus_arbiter (BusFunction function)
	Return a Cerata model of a BusArbiter. More...

std::shared_ptr< Component >	BusReadSerializer ()
	Return a BusReadSerializer component.

bool	operator== (const BusSpec &lhs, const BusSpec &rhs)
	Returns true if BusSpecs are equal.

std::shared_ptr< Type >	bus (const BusSpecParams &param)
	Fletcher bus type with access mode conveyed through spec of params.

std::shared_ptr< BusPort >	bus_port (const std::string &name, Port::Dir dir, const BusSpecParams &params)
	Make a new port and return a shared pointer to it.

std::shared_ptr< BusPort >	bus_port (Port::Dir dir, const BusSpecParams &params)
	Make a new port, name it automatically based on the bus parameters, and return a shared pointer to it.

void	ConnectBusParam (cerata::Graph dst, const std::string &prefix, const BusDimParams &src, cerata::NodeMap rebinding)
	Find and connect all prefixed bus params on a graph to the supplied source params, and append a rebind map.

bool	operator== (const BusDim &lhs, const BusDim &rhs)
	Returns true if BusDims are equal.

std::shared_ptr< Component >	BusWriteSerializer ()
	Return a BusWriteSerializer component.

auto	external () -> std::optional< std::shared_ptr< cerata::Type >>

int	fletchgen (int argc, char **argv)
	Fletchgen main entry. Used to wrap into PyFletchgen.

std::shared_ptr< Kernel >	kernel (const std::string &name, const std::vector< std::shared_ptr< RecordBatch >> &recordbatches, const std::shared_ptr< Component > &mmio)
	Make a kernel component based on RecordBatch and MMIO components. More...

std::shared_ptr< Mantle >	mantle (const std::string &name, const std::vector< std::shared_ptr< RecordBatch >> &recordbatches, const std::shared_ptr< Nucleus > &nucleus, BusDim bus_spec, Axi4LiteSpec axi_spec)
	Construct a Mantle and return a shared pointer to it. More...

std::shared_ptr< MmioPort >	mmio_port (Port::Dir dir, const MmioReg &reg, const std::shared_ptr< ClockDomain > &domain=cerata::default_domain())
	Create an mmio port.

std::shared_ptr< Component >	mmio (const std::vector< fletcher::RecordBatchDescription > &batches, const std::vector< MmioReg > &regs, Axi4LiteSpec axi_spec)
	Generate the MMIO component for the nucleus. More...

std::string	GenerateVhdmmioYaml (const std::vector< std::vector< MmioReg > * > &regs, Axi4LiteSpec axi_spec, std::optional< size_t * > next_addr=std::nullopt)
	Returns a YAML string for the vhdmmio tool based on a set of registers. More...

bool	ExposeToKernel (MmioFunction fun)
	Return true if an mmio register's function must cause it to be exposed to the user kernel.

Component *	accm ()
	Return the ArrayCmdCtrlMerger component.

std::shared_ptr< Nucleus >	nucleus (const std::string &name, const std::vector< std::shared_ptr< RecordBatch >> &recordbatches, const std::shared_ptr< Kernel > &kernel, const std::shared_ptr< Component > &mmio, Axi4LiteSpec axi_spec)
	Make an Nucleus component based on RecordBatch components. Returns a shared pointer to the new Nucleus.

std::vector< MmioReg >	GetProfilingRegs (const std::vector< std::shared_ptr< RecordBatch >> &recordbatches)
	Obtain the registers that should be reserved in the mmio component for profiling.

std::shared_ptr< cerata::Type >	stream_probe (const std::shared_ptr< Node > &count_width)
	Returns a stream probe type based on a count width for multi-epc streams.

NodeProfilerPorts	EnableStreamProfiling (cerata::Component comp, const std::vector< cerata::Signal > &profile_nodes)
	Transforms a Cerata component graph to include stream profilers for selected nodes. More...

std::unique_ptr< cerata::Instance >	profiler (const std::string &name, cerata::NodeMap *rebinding, const std::shared_ptr< cerata::ClockDomain > &domain=kernel_cd())
	Returns an instance of a StreamProfiler.

std::shared_ptr< RecordBatch >	record_batch (const std::string &name, const std::shared_ptr< FletcherSchema > &fletcher_schema, const fletcher::RecordBatchDescription &batch_desc)
	Make a new RecordBatch(Reader/Writer) component, based on a Fletcher schema.

std::shared_ptr< FieldPort >	arrow_port (const std::shared_ptr< FletcherSchema > &fletcher_schema, const std::shared_ptr< arrow::Field > &field, bool reverse, const std::shared_ptr< ClockDomain > &domain=default_domain())
	Construct a field-derived port for Arrow data. More...

std::shared_ptr< FieldPort >	command_port (const std::shared_ptr< FletcherSchema > &schema, const std::shared_ptr< arrow::Field > &field, const std::shared_ptr< Node > &index_width, const std::shared_ptr< Node > &tag_width, std::optional< std::shared_ptr< Node >> addr_width=std::nullopt, const std::shared_ptr< ClockDomain > &domain=default_domain())
	Construct a field-derived command port. More...

std::shared_ptr< FieldPort >	unlock_port (const std::shared_ptr< FletcherSchema > &schema, const std::shared_ptr< arrow::Field > &field, const std::shared_ptr< Node > &tag_width, const std::shared_ptr< ClockDomain > &domain=default_domain())
	Construct a field-derived unlock port. More...

void	write_static_vhdl (const std::string &real_dir, const std::string &emb_dir="hardware")
	Writes Fletcher's static VHDL files to the given directory. More...

std::string	GetProgramName (char *argv0)
	Return the name of this program executable.

cerata::Port::Dir	mode2dir (fletcher::Mode mode)
	Return a Cerata port direction from a Fletcher access mode.

void	LogCerata (cerata::LogLevel level, std::string const &message, char const source_function, char const source_file, int line_number)
	Callback function for the Cerata logger. More...

std::string	version ()
	Return Fletchgen version string.

Variables
constexpr char	MMIO_DEFAULT [] = "fletchgen_mmio_default"
	Fletchgen metadata for mmio-controlled buffer address ports.

constexpr char	MMIO_BATCH [] = "fletchgen_mmio_batch"
	Fletchgen metadata for mmio-controlled buffer address ports.

constexpr char	MMIO_BUFFER [] = "fletchgen_mmio_buffer"
	Fletchgen metadata for mmio-controlled buffer address ports.

constexpr char	MMIO_KERNEL [] = "fletchgen_mmio_kernel"
	Fletchgen metadata for mmio-controlled kernel ports.

constexpr char	MMIO_PROFILE [] = "fletchgen_mmio_profile"
	Fletchgen metadata for mmio-controlled profiling ports.

constexpr char	DEFAULT_NOTICE []
	Default copyright notice. More...

Detailed Description

Contains all classes and functions related to Fletchgen.

Enumeration Type Documentation

◆ BusFunction

enum fletchgen::BusFunction

strong

Defines function of a bus interface (read/write).

Enumerator
READ	Interface reads from memory.
WRITE	Interface writes to memory.

Definition at line 42 of file bus.h.

◆ ConfigType

enum fletchgen::ConfigType

strong

Types for ArrayReader/Writer configuration string.

Enumerator
ARB	Arbiter level.
NUL	Null bitmap.
PRIM	Primitive (fixed-width) fields.
LIST	Variable length fields.
LIST_PRIM	List of primitives. Can have EPC > 1.
STRUCT	Structs, composed of multiple fields.

Definition at line 62 of file array.h.

◆ MmioBehavior

enum fletchgen::MmioBehavior

strong

Register access behavior enumeration.

Enumerator
CONTROL	Register contents is controlled by host software.
STATUS	Register contents is controlled by hardware kernel.
STROBE	Register contents is asserted for one cycle by host software.

Definition at line 61 of file mmio.h.

◆ MmioFunction

enum fletchgen::MmioFunction

strong

Register intended use enumeration.

Enumerator
DEFAULT	Default registers.
BATCH	Registers for RecordBatch metadata.
BUFFER	Registers for buffer addresses.
KERNEL	Registers for the kernel.
PROFILE	Register for the profiler.

Definition at line 52 of file mmio.h.

Function Documentation

◆ array() [1/2]

Component* fletchgen::array ( fletcher::Mode mode )

Return a Cerata component model of an ArrayReader/Writers.

Parameters

mode	Whether the Array(Reader/Writer) instance must READ from memory or WRITE to memory.

Returns: A unique pointer holding the Array(Reader/Writer) instance.

◆ array() [2/2]

Component* fletchgen::array ( Mode mode )

Return a Cerata component model of an Array(Reader/Writer).

This model corresponds to either: hardware/arrays/ArrayReader.vhd or hardware/arrays/ArrayWriter.vhd depending on the mode parameter.

Changes to the implementation of this component in the HDL source must be reflected in the implementation of this function.

WARNING: Binding of the input/output data stream width generics is more arcane than what is good for most. As such, most widths are just bound to some integer literals rather than parameters. Any code instantiating this component should rebind the type themselves after figuring out their true width.

Parameters

mode	Whether this Array component must Read or Write.

Returns: The component model.

Definition at line 139 of file array.cc.

◆ arrow_port()

std::shared_ptr< FieldPort > fletchgen::arrow_port	(	const std::shared_ptr< FletcherSchema > &	fletcher_schema,
		const std::shared_ptr< arrow::Field > &	field,
		bool	reverse,
		const std::shared_ptr< ClockDomain > &	domain = `default_domain()`
	)

Construct a field-derived port for Arrow data.

Parameters

fletcher_schema	The Fletcher-derived schema.
field	The Arrow field to derive the port from.
reverse	Reverse the direction of the port.
domain	The clock domain of this port.

Returns: A shared pointer to a new FieldPort.

Definition at line 199 of file recordbatch.cc.

◆ axi4_lite()

std::shared_ptr< Axi4LitePort > fletchgen::axi4_lite	(	Port::Dir	dir,
		const std::shared_ptr< ClockDomain > &	domain = `cerata::default_domain()`,
		Axi4LiteSpec	spec = `Axi4LiteSpec()`
	)

Make a new AXI4-lite port, returning a shared pointer to it.

Parameters

dir	The direction of the port.
spec	The specification of the port.
domain	The clock domain.

Returns: A shared pointer to the new port.

Definition at line 67 of file axi4_lite.cc.

◆ bus_arbiter()

Component * fletchgen::bus_arbiter ( BusFunction function )

Return a Cerata model of a BusArbiter.

Parameters

function The function of the bus; either read or write.

Returns: A Bus(Read/Write)Arbiter Cerata component model.

This model corresponds to either: hardware/interconnect/BusReadArbiterVec.vhd or hardware/interconnect/BusWriteArbiterVec.vhd depending on the function parameter.

Changes to the implementation of this component in the HDL source must be reflected in the implementation of this function.

Definition at line 82 of file bus.cc.

◆ command_port()

std::shared_ptr< FieldPort > fletchgen::command_port	(	const std::shared_ptr< FletcherSchema > &	schema,
		const std::shared_ptr< arrow::Field > &	field,
		const std::shared_ptr< Node > &	index_width,
		const std::shared_ptr< Node > &	tag_width,
		std::optional< std::shared_ptr< Node >>	addr_width = `std::nullopt`,
		const std::shared_ptr< ClockDomain > &	domain = `default_domain()`
	)

Construct a field-derived command port.

Parameters

schema	The Fletcher-derived schema.
field	The Arrow field to derive the port from.
index_width	Type generic node for index field width.
tag_width	Type generic node for tag field width.
addr_width	Optionally, width of addresses in the ctrl field. If not used, no ctrl field is generated.
domain	The clock domain.

Returns: A shared pointer to a new FieldPort.

Definition at line 218 of file recordbatch.cc.

◆ ConvertFixedWidthType()

std::shared_ptr< Type > fletchgen::ConvertFixedWidthType	(	const std::shared_ptr< arrow::DataType > &	arrow_type,
		int	epc = `1`
	)

Convert a fixed-width arrow::DataType to a fixed-width Fletcher Type.

Does not take into consideration nesting.

Parameters

arrow_type The arrow::DataType.

Returns: The corresponding Type

Definition at line 148 of file basic_types.cc.

◆ EnableStreamProfiling()

NodeProfilerPorts fletchgen::EnableStreamProfiling	(	cerata::Component *	comp,
		const std::vector< cerata::Signal * > &	profile_nodes
	)

Transforms a Cerata component graph to include stream profilers for selected nodes.

To select a node for profiling, the node must be of type cerata::Stream and it must have the PROFILE_KEY set to true in its kv-metadata.

Currently doesn't make a deep copy, so it modifies the existing structure irreversibly.

Parameters

comp	The component to apply the transformation to.
profile_nodes	The signal nodes that should be profiled.

Returns: A mapping from each input node to the instantiated profiler and its relevant result port nodes.

Definition at line 155 of file profiler.cc.

◆ GenerateConfigString()

std::string fletchgen::GenerateConfigString	(	const arrow::Field &	field,
		int	level = `0`
	)

Return the configuration string for a ArrayReader/Writer.

Parameters

field	The arrow::Field to derive the string from.
level	Nesting level for recursive calls to this function.

Returns: The string.

Definition at line 256 of file array.cc.

◆ GenerateVhdmmioYaml()

std::string fletchgen::GenerateVhdmmioYaml	(	const std::vector< std::vector< MmioReg > * > &	regs,
		Axi4LiteSpec	axi_spec,
		std::optional< size_t * >	next_addr = `std::nullopt`
	)

Returns a YAML string for the vhdmmio tool based on a set of registers.

Any fixed addresses in the MmioReg.address field can only occur at the start of the vector set and must be ordered.

Parameters

regs	A vector of pointers to vectors of registers. Will be modified in case address was not set.
axi_spec	Specification of the AXI4 lite mmio bus.
next_addr	Optionally outputs the byte address offset of the next free register address.

Definition at line 99 of file mmio.cc.

◆ GetArrayDataSpec()

std::pair< uint32_t, uint32_t > fletchgen::GetArrayDataSpec ( const arrow::Field & arrow_field )

Get the ArrayR/W number of streams and data width from an Arrow Field.

Parameters

arrow_field The field

Returns: A tuple containing the {no. streams, full data width}.

Definition at line 478 of file array.cc.

◆ GetClockResetPort()

std::optional< cerata::Port * > fletchgen::GetClockResetPort	(	cerata::Graph *	graph,
		const ClockDomain &	domain
	)

Return the clock/reset port of a graph for a specific clock domain, if it exists.

Parameters

graph	The graph to find the port for.
domain	The domain to find the port for.

Returns: Optionally, the port node that holds the clock/reset record.

Definition at line 181 of file basic_types.cc.

◆ GetConfigType()

ConfigType fletchgen::GetConfigType ( const arrow::DataType & type )

Return the configuration string type version of an arrow::DataType.

Parameters

type	The arrow::DataType.

Returns: The equivalent ConfigType.

Definition at line 188 of file array.cc.

◆ GetFixedWidthTypeBitWidth()

int fletchgen::GetFixedWidthTypeBitWidth ( const arrow::DataType & arrow_type )

Returns the bit-width of a fixed-width Arrow type. Throws if it's not a fixed-width type.

Parameters

arrow_type The type to inspect.

Returns: The bit width of the fixed type.

Definition at line 140 of file basic_types.cc.

◆ GetStreamType()

std::shared_ptr< Type > fletchgen::GetStreamType	(	const arrow::Field &	arrow_field,
		fletcher::Mode	mode,
		int	level = `0`
	)

Convert an Arrow::Field into a stream type.

Parameters

arrow_field	The Arrow::Field to convert.
mode	Whether this stream is used for reading or writing.
level	Nesting level.

Returns: The Stream Type.

Definition at line 369 of file array.cc.

◆ GetStreamTypeMapper()

std::shared_ptr< TypeMapper > fletchgen::GetStreamTypeMapper	(	Type *	stream_type,
		Type *	other
	)

Get a type mapper for an Arrow::Field-based stream to an ArrayReader/Writer stream.

These type mappers can be automatically deduced based on the generic Fletcher types being used.

Parameters

stream_type	The type typically generated with GetStreamType()
other	The other type, typically some read_data() or write_data() generated type.

Returns: A type mapper

Definition at line 323 of file array.cc.

◆ GetWidthNode()

std::shared_ptr< Node > fletchgen::GetWidthNode ( const arrow::DataType & type )

Return a node representing the width of a (flat) Arrow DataType.

Parameters

type	The arrow::DataType.

Returns: A Literal Node representing the width.

Definition at line 209 of file array.cc.

◆ kernel()

std::shared_ptr< Kernel > fletchgen::kernel	(	const std::string &	name,
		const std::vector< std::shared_ptr< RecordBatch >> &	recordbatches,
		const std::shared_ptr< Component > &	mmio
	)

Make a kernel component based on RecordBatch and MMIO components.

Parameters

name	The name of the kernel.
recordbatches	The recordbatch components to base the kernel on.
mmio	The MMIO component to base the kernel on.

Returns: A shared pointer to the new kernel component.

Definition at line 93 of file kernel.cc.

◆ LogCerata()

void fletchgen::LogCerata	(	cerata::LogLevel	level,
		std::string const &	message,
		char const *	source_function,
		char const *	source_file,
		int	line_number
	)

Callback function for the Cerata logger.

Parameters

level	The logging level.
message	The message.
source_function	The source code line.
source_file	The source code file.
line_number	The line number.

Definition at line 43 of file utils.cc.

◆ mantle()

std::shared_ptr< Mantle > fletchgen::mantle	(	const std::string &	name,
		const std::vector< std::shared_ptr< RecordBatch >> &	recordbatches,
		const std::shared_ptr< Nucleus > &	nucleus,
		BusDim	bus_spec,
		Axi4LiteSpec	axi_spec
	)

Construct a Mantle and return a shared pointer to it.

Construct the mantle component and return a shared pointer to it.

Parameters

name	The name of the mantle.
recordbatches	The RecordBatch components to instantiate.
nucleus	The Nucleus to instantiate.
bus_spec	The specification of the top-level bus.
axi_spec	The specification of the AXI4-lite MMIO interface.

Returns: A shared pointer to the mantle component.

Definition at line 189 of file mantle.cc.

◆ mmio()

std::shared_ptr< Component > fletchgen::mmio	(	const std::vector< fletcher::RecordBatchDescription > &	batches,
		const std::vector< MmioReg > &	regs,
		Axi4LiteSpec	axi_spec
	)

Generate the MMIO component for the nucleus.

Must generate the component in such a way that GenerateVhdmmioYaml in combination with the vhdmmio tool creates an identical component interface.

Parameters

[in]	batches	The RecordBatchDescriptions of the recordbatches in the design.
[in]	regs	A list of custom 32-bit register names.
[in]	axi_spec	Specification of the AXI4-lite interface

Returns: A component.

Definition at line 62 of file mmio.cc.

◆ unlock_port()

std::shared_ptr< FieldPort > fletchgen::unlock_port	(	const std::shared_ptr< FletcherSchema > &	schema,
		const std::shared_ptr< arrow::Field > &	field,
		const std::shared_ptr< Node > &	tag_width,
		const std::shared_ptr< ClockDomain > &	domain = `default_domain()`
	)

Construct a field-derived unlock port.

Parameters

schema	The Fletcher-derived schema.
field	The Arrow field to derive the port from.
tag_width	The width of the tag field.
domain	The clock domain.

Returns: A shared pointer to a new FieldPort.

Definition at line 235 of file recordbatch.cc.

◆ write_static_vhdl()

void fletchgen::write_static_vhdl	(	const std::string &	real_dir,
		const std::string &	emb_dir = `"hardware"`
	)

Writes Fletcher's static VHDL files to the given directory.

Parameters

real_dir	The real directory to write to.
emb_dir	The embedded filesystem directory to read from, defaulting to the toplevel resource directory ("hardware").

Definition at line 27 of file static_vhdl.cc.

Variable Documentation

◆ DEFAULT_NOTICE

constexpr char fletchgen::DEFAULT_NOTICE[]

constexpr

Initial value:

= "-- Copyright 2018-2019 Delft University of Technology\n"
                                  "--\n"
                                  "-- Licensed under the Apache License, Version 2.0 (the \"License\");\n"
                                  "-- you may not use this file except in compliance with the License.\n"
                                  "-- You may obtain a copy of the License at\n"
                                  "--\n"
                                  "--     http://www.apache.org/licenses/LICENSE-2.0\n"
                                  "--\n"
                                  "-- Unless required by applicable law or agreed to in writing, software\n"
                                  "-- distributed under the License is distributed on an \"AS IS\" BASIS,\n"
                                  "-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n"
                                  "-- See the License for the specific language governing permissions and\n"
                                  "-- limitations under the License.\n"
                                  "--\n"
                                  "-- This file was generated by Fletchgen. Modify this file at your own risk.\n"
                                  "\n"

Default copyright notice.

Definition at line 46 of file utils.h.

Namespaces

Classes

Typedefs

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ BusFunction

◆ ConfigType

◆ MmioBehavior

◆ MmioFunction

Function Documentation

◆ array() [1/2]

◆ array() [2/2]

◆ arrow_port()

◆ axi4_lite()

◆ bus_arbiter()

◆ command_port()

◆ ConvertFixedWidthType()

◆ EnableStreamProfiling()

◆ GenerateConfigString()

◆ GenerateVhdmmioYaml()

◆ GetArrayDataSpec()

◆ GetClockResetPort()

◆ GetConfigType()

◆ GetFixedWidthTypeBitWidth()

◆ GetStreamType()

◆ GetStreamTypeMapper()

◆ GetWidthNode()

◆ kernel()

◆ LogCerata()

◆ mantle()

◆ mmio()

◆ unlock_port()

◆ write_static_vhdl()

Variable Documentation

◆ DEFAULT_NOTICE