An AXI4-lite port derived from an AXI4-lite specification. More...
#include <axi4_lite.h>
Inheritance diagram for fletchgen::Axi4LitePort:
Collaboration diagram for fletchgen::Axi4LitePort:
Public Member Functions | |
| Axi4LitePort (Port::Dir dir, Axi4LiteSpec spec, std::string name="mmio", std::shared_ptr< ClockDomain > domain=cerata::default_domain()) | |
| Construct a new MmioPort. | |
| std::shared_ptr< Object > | Copy () const override |
| Make a copy of this AXI4-lite port. | |
Public Attributes | |
| Axi4LiteSpec | spec_ |
| The specification this port was derived from. | |
Detailed Description
An AXI4-lite port derived from an AXI4-lite specification.
Definition at line 49 of file axi4_lite.h.
The documentation for this struct was generated from the following files:
- src/fletchgen/axi4_lite.h
- src/fletchgen/axi4_lite.cc
