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Cerata
A library to generate structural hardware designs
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19 #include "cerata/graph.h"
20 #include "cerata/vhdl/declaration.h"
21 #include "cerata/vhdl/block.h"
44 auto objs = comp.
GetAll<T>();
45 for (
const auto &o : objs) {
48 if (decl.lines.size() > 1) {
59 auto objs = comp.
GetAll<T>();
60 for (
const auto &o : objs) {
63 if (assignment.lines.size() > 1) {
std::vector< T * > GetAll() const
Get all objects of a specific type.
An array of signal nodes.
A structure to hold multiple blocks.
static Block Generate(const Parameter &par, int depth=0)
Generate a parameter declaration as VHDL generic.
static Block GenerateAssignments(const Component &comp, int indent=0)
Generate relevant VHDL signal assignments of all Cerata nodes.
static Block GenerateNodeDeclarations(const Component &comp, int indent=0)
Generate relevant VHDL component declarations of all Cerata instances.
static MultiBlock GenerateCompDeclarations(const Component &comp, int indent=0)
Generate component declarations within VHDL architecture declarations block.
static MultiBlock Generate(const Component &comp)
Generate the VHDL architecture of a component.
static MultiBlock GenerateCompInstantiations(const Component &comp, int indent=0)
Generate component instantiations within VHDL architecture concurrent statements block.
A port is a terminator node on a graph.
Block & AppendBlankLineIfNotEmpty()
Append a blank line if the block is not empty.
std::shared_ptr< Port > port(const std::string &name, const std::shared_ptr< Type > &type, Term::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Make a new port with some name, type and direction.
Contains everything related to the VHDL back-end.