Cerata
A library to generate structural hardware designs
architecture.h
1 // Copyright 2018-2019 Delft University of Technology
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #pragma once
16 
17 #include <memory>
18 
19 #include "cerata/graph.h"
20 #include "cerata/vhdl/declaration.h"
21 #include "cerata/vhdl/block.h"
22 
23 namespace cerata::vhdl {
24 
26 struct Arch {
28  static MultiBlock Generate(const Component &comp);
30  static Block Generate(const Signal &sig, int indent = 0);
32  static Block Generate(const Port &port, int indent = 0);
34  static Block Generate(const SignalArray &sig_array, int indent = 0);
36  static MultiBlock GenerateCompDeclarations(const Component &comp, int indent = 0);
38  static MultiBlock GenerateCompInstantiations(const Component &comp, int indent = 0);
39 
41  template<typename T>
42  static Block GenerateNodeDeclarations(const Component &comp, int indent = 0) {
43  Block result(indent);
44  auto objs = comp.GetAll<T>();
45  for (const auto &o : objs) {
46  auto decl = Decl::Generate(*o, 1);
47  result << decl;
48  if (decl.lines.size() > 1) {
49  result << Line();
50  }
51  }
52  return result.AppendBlankLineIfNotEmpty();
53  }
54 
56  template<typename T>
57  static Block GenerateAssignments(const Component &comp, int indent = 0) {
58  Block result(indent);
59  auto objs = comp.GetAll<T>();
60  for (const auto &o : objs) {
61  auto assignment = Arch::Generate(*o, 1);
62  result << assignment;
63  if (assignment.lines.size() > 1) {
64  result << Line();
65  }
66  }
67  return result.AppendBlankLineIfNotEmpty();
68  }
69 };
70 
71 } // namespace cerata::vhdl
cerata::Component
A Component graph.
Definition: graph.h:158
cerata::Graph::GetAll
std::vector< T * > GetAll() const
Get all objects of a specific type.
Definition: graph.h:63
cerata::SignalArray
An array of signal nodes.
Definition: array.h:100
cerata::vhdl::MultiBlock
A structure to hold multiple blocks.
Definition: block.h:77
cerata::vhdl::Arch
Architecture generators.
Definition: architecture.h:26
cerata::Signal
A Signal Node.
Definition: signal.h:30
cerata::vhdl::Line
A line of code.
Definition: block.h:25
cerata::vhdl::Decl::Generate
static Block Generate(const Parameter &par, int depth=0)
Generate a parameter declaration as VHDL generic.
Definition: declaration.cc:72
cerata::vhdl::Arch::GenerateAssignments
static Block GenerateAssignments(const Component &comp, int indent=0)
Generate relevant VHDL signal assignments of all Cerata nodes.
Definition: architecture.h:57
cerata::vhdl::Block
A block of code.
Definition: block.h:50
cerata::vhdl::Arch::GenerateNodeDeclarations
static Block GenerateNodeDeclarations(const Component &comp, int indent=0)
Generate relevant VHDL component declarations of all Cerata instances.
Definition: architecture.h:42
cerata::vhdl::Arch::GenerateCompDeclarations
static MultiBlock GenerateCompDeclarations(const Component &comp, int indent=0)
Generate component declarations within VHDL architecture declarations block.
Definition: architecture.cc:33
cerata::vhdl::Arch::Generate
static MultiBlock Generate(const Component &comp)
Generate the VHDL architecture of a component.
Definition: architecture.cc:61
cerata::vhdl::Arch::GenerateCompInstantiations
static MultiBlock GenerateCompInstantiations(const Component &comp, int indent=0)
Generate component instantiations within VHDL architecture concurrent statements block.
Definition: architecture.cc:50
cerata::Port
A port is a terminator node on a graph.
Definition: port.h:57
cerata::vhdl::Block::AppendBlankLineIfNotEmpty
Block & AppendBlankLineIfNotEmpty()
Append a blank line if the block is not empty.
Definition: block.cc:99
cerata::port
std::shared_ptr< Port > port(const std::string &name, const std::shared_ptr< Type > &type, Term::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Make a new port with some name, type and direction.
Definition: port.cc:22
cerata::vhdl
Contains everything related to the VHDL back-end.
Definition: architecture.cc:31