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Cerata
A library to generate structural hardware designs
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28 explicit Line(
const std::string &str) {
36 if (
parts.size() == 1) {
37 if (
parts[0] ==
"\n") {
44 [[nodiscard]] std::string
ToString()
const;
65 Block &
Sort(std::optional<char> c = std::nullopt);
68 [[nodiscard]] std::string
ToString()
const;
81 [[nodiscard]] std::string
ToString()
const;
110 Block &
Prepend(
const std::string &lhs,
Block *rhs,
const std::string &sep =
"_");
122 std::string
ToString(
const std::vector<Block> &blocks);
std::vector< std::string > parts
The parts of the line of code.
A structure to hold multiple blocks.
std::vector< Line > lines
Lines in the blocks.
MultiBlock(int indent=0)
Multiblock constructor.
std::string ToString() const
Return this block as a single string.
std::vector< Block > blocks
The blocks in this multiblock.
std::string ToString() const
Return the line as a single string.
Block & operator<<=(Block &lhs, const std::string &rhs)
Append a string to the last parts of all lines in a block, except the last one.
Block & Prepend(const std::string &lhs, Block *rhs, const std::string &sep)
Prepend a string to every line of a block.
Line & operator+=(Line &lhs, const std::string &str)
Append a string to the last line part.
Line(const std::string &str)
Line constructor.
Block(int indent=0)
Block constructor.
std::string ToString(const std::vector< Block > &blocks)
Return a vector of blocks as a single string.
std::string ToString() const
Return this multiblock as a single string.
Line & operator<<(Line &lhs, const std::string &str)
Append a part to a line.
Block & Sort(std::optional< char > c=std::nullopt)
Sort the lines in the block. Supply a character to stop sorting per line after encountering the chara...
int indent
Indenting level of the block.
Block & Reverse()
Return the block in reverse.
std::vector< size_t > GetAlignments() const
Return the alignment for each line.
bool IsBlank() const
Return true if line is blank.
Block & AppendBlankLineIfNotEmpty()
Append a blank line if the block is not empty.
Contains everything related to the VHDL back-end.