cerata::vhdl::Arch Struct Reference

Architecture generators. More...

#include <architecture.h>

Static Public Member Functions
static MultiBlock	Generate (const Component &comp)
	Generate the VHDL architecture of a component.
static Block	Generate (const Signal &sig, int indent=0)
	Generate the VHDL signal assignments.
static Block	Generate (const Port &port, int indent=0)
	Generate the VHDL port assignments.
static Block	Generate (const SignalArray &sig_array, int indent=0)
	Generate the VHDL signal array assignments inside a component.
static MultiBlock	GenerateCompDeclarations (const Component &comp, int indent=0)
	Generate component declarations within VHDL architecture declarations block.
static MultiBlock	GenerateCompInstantiations (const Component &comp, int indent=0)
	Generate component instantiations within VHDL architecture concurrent statements block.
template<typename T >
static Block	GenerateNodeDeclarations (const Component &comp, int indent=0)
	Generate relevant VHDL component declarations of all Cerata instances.
template<typename T >
static Block	GenerateAssignments (const Component &comp, int indent=0)
	Generate relevant VHDL signal assignments of all Cerata nodes.

Detailed Description

Architecture generators.

Definition at line 26 of file architecture.h.

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The documentation for this struct was generated from the following files:

• src/cerata/vhdl/architecture.h
• src/cerata/vhdl/architecture.cc