17 #include <arrow/api.h>
30 std::vector<std::shared_ptr<arrow::Schema>>
schemas;
38 std::vector<std::string>
languages = {
"vhdl",
"dot"};
46 std::vector<std::string>
regs;
50 std::vector<std::string>
bus_dims = {
"64,512,8,1,16"};
88 static bool Parse(
Options *options,
int argc,
char **argv);
97 [[nodiscard]]
bool MustGenerate(
const std::string &target)
const;
105 [[nodiscard]] std::string
ToString()
const;
Contains all classes and functions related to Fletchgen.
Fletcher program options.
bool quit
Whether to quit the program without doing anything (useful for just showing help or version).
std::string output_dir
Output directory.
bool LoadSchemas()
Load all specified Schemas. Returns true if successful, false otherwise.
std::vector< std::shared_ptr< arrow::Schema > > schemas
Loaded schemas.
bool MustGenerateDesign() const
Return true if a design must be generated.
bool LoadRecordBatches()
Load all specified RecordBatches. Returns true if successful, false otherwise.
std::vector< std::string > languages
Output languages.
bool axi_top
Whether to generate an AXI top level.
bool MustGenerateSREC() const
Return true if an SREC file must be generated.
std::vector< std::string > recordbatch_paths
Paths to RecordBatches.
std::string srec_out_path
SREC output path. This is the path where an SREC file based on input RecordBatches will be placed.
bool mmio64
Use 64-bits data width for AXI4-lite MMIO bus when true.
bool backup
Whether to backup any existing generated files.
bool static_vhdl
Whether to generate static VHDL files (copied from hardware directory, embedded as resources).
bool version
Show version information.
static bool Parse(Options *options, int argc, char **argv)
Parse command line options and store the result.
std::vector< std::string > schema_paths
Paths to the schema files.
std::vector< std::string > bus_dims
Bus dimensions strings.
bool quiet
Make the output quiet. TODO(johanpel): not yet implemented.
size_t mmio_addr_width
AXI4-lite address bus width.
std::string srec_sim_dump
SREC simulation output path, where the simulation should dump the memory contents of written RecordBa...
bool sim_top
Whether to simulate an AXI top level.
bool MustGenerate(const std::string &target) const
Return true if generation must take place for some target.
std::string externals_yaml
File to parse for external signals to/from top level to kernel.
std::vector< std::string > regs
Custom 32-bit registers.
std::vector< std::shared_ptr< arrow::RecordBatch > > recordbatches
Loaded RecordBatches.
bool verbose
Make the output verbose. TODO(johanpel): not yet implemented.
size_t mmio_offset
AXI4-lite offset address for Fletcher registers.
std::string ToString() const
Return human-readable options.
bool vivado_hls
Vivado HLS template. TODO(johanpel): not yet implemented.
std::string kernel_name
Name of the Kernel.