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Cerata
A library to generate structural hardware designs
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22 #include "cerata/node.h"
23 #include "cerata/type.h"
24 #include "cerata/graph.h"
26 #include "cerata/vhdl/block.h"
27 #include "cerata/vhdl/vhdl_types.h"
A structure to hold multiple blocks.
A graph representing a hardware structure.
static Block GeneratePortArrayMaps(const PortArray &array)
Generate an associativity list for an instantiated PortArray.
static Block GeneratePortMaps(const Port &port, bool full_array=false)
Generate an associativity list for an instantiated Port.
static MultiBlock Generate(const Graph &graph)
Generate a VHDL instantiation of a graph.
Functions to generate VHDL instantiation code.
static Block GenerateGenericMap(const Parameter &par)
Generate an associativity list for an instantiated Parameter.
A port is a terminator node on a graph.
std::shared_ptr< Port > port(const std::string &name, const std::shared_ptr< Type > &type, Term::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Make a new port with some name, type and direction.
Contains everything related to the VHDL back-end.