Cerata
A library to generate structural hardware designs
instantiation.h
1 // Copyright 2018-2019 Delft University of Technology
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #pragma once
16 
17 #include <algorithm>
18 #include <string>
19 #include <memory>
20 #include <vector>
21 
22 #include "cerata/node.h"
23 #include "cerata/type.h"
24 #include "cerata/graph.h"
25 
26 #include "cerata/vhdl/block.h"
27 #include "cerata/vhdl/vhdl_types.h"
28 
29 namespace cerata::vhdl {
30 
32 struct Inst {
34  static MultiBlock Generate(const Graph &graph);
36  static Block GeneratePortMaps(const Port &port, bool full_array = false);
38  static Block GeneratePortArrayMaps(const PortArray &array);
40  static Block GenerateGenericMap(const Parameter &par);
41 };
42 
43 } // namespace cerata::vhdl
cerata::vhdl::MultiBlock
A structure to hold multiple blocks.
Definition: block.h:77
cerata::Graph
A graph representing a hardware structure.
Definition: graph.h:37
cerata::vhdl::Inst::GeneratePortArrayMaps
static Block GeneratePortArrayMaps(const PortArray &array)
Generate an associativity list for an instantiated PortArray.
Definition: instantiation.cc:214
cerata::vhdl::Inst::GeneratePortMaps
static Block GeneratePortMaps(const Port &port, bool full_array=false)
Generate an associativity list for an instantiated Port.
Definition: instantiation.cc:181
cerata::vhdl::Inst::Generate
static MultiBlock Generate(const Graph &graph)
Generate a VHDL instantiation of a graph.
Definition: instantiation.cc:246
cerata::vhdl::Inst
Functions to generate VHDL instantiation code.
Definition: instantiation.h:32
cerata::Parameter
A Parameter node.
Definition: parameter.h:29
cerata::vhdl::Block
A block of code.
Definition: block.h:50
cerata::PortArray
An array of port nodes.
Definition: array.h:123
cerata::vhdl::Inst::GenerateGenericMap
static Block GenerateGenericMap(const Parameter &par)
Generate an associativity list for an instantiated Parameter.
Definition: instantiation.cc:60
cerata::Port
A port is a terminator node on a graph.
Definition: port.h:57
cerata::port
std::shared_ptr< Port > port(const std::string &name, const std::shared_ptr< Type > &type, Term::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Make a new port with some name, type and direction.
Definition: port.cc:22
cerata::vhdl
Contains everything related to the VHDL back-end.
Definition: architecture.cc:31