Cerata
A library to generate structural hardware designs
declaration.h
1 // Copyright 2018-2019 Delft University of Technology
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #pragma once
16 
17 #include <algorithm>
18 #include <string>
19 #include <memory>
20 
21 #include "cerata/node.h"
22 #include "cerata/type.h"
23 #include "cerata/graph.h"
24 
25 #include "cerata/vhdl/block.h"
26 
27 namespace cerata::vhdl {
28 
30 struct Decl {
32  static Block Generate(const Parameter &par, int depth = 0);
34  static Block Generate(const Port &port, int depth = 0);
36  static Block Generate(const PortArray &port_array, int depth = 0);
38  static Block Generate(const Signal &sig, int depth = 0);
40  static Block Generate(const SignalArray &sig_array, int depth = 0);
42  static MultiBlock Generate(const Component &comp, bool entity = false, int indent = 1);
43 };
44 
45 } // namespace cerata::vhdl
cerata::Component
A Component graph.
Definition: graph.h:158
cerata::SignalArray
An array of signal nodes.
Definition: array.h:100
cerata::vhdl::MultiBlock
A structure to hold multiple blocks.
Definition: block.h:77
cerata::Signal
A Signal Node.
Definition: signal.h:30
cerata::vhdl::Decl::Generate
static Block Generate(const Parameter &par, int depth=0)
Generate a parameter declaration as VHDL generic.
Definition: declaration.cc:72
cerata::Parameter
A Parameter node.
Definition: parameter.h:29
cerata::vhdl::Block
A block of code.
Definition: block.h:50
cerata::PortArray
An array of port nodes.
Definition: array.h:123
cerata::vhdl::Decl
Declaration generators.
Definition: declaration.h:30
cerata::port_array
std::shared_ptr< PortArray > port_array(const std::string &name, const std::shared_ptr< Type > &type, const std::shared_ptr< Node > &size, Port::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Get a smart pointer to a new ArrayPort.
Definition: array.cc:175
cerata::Port
A port is a terminator node on a graph.
Definition: port.h:57
cerata::port
std::shared_ptr< Port > port(const std::string &name, const std::shared_ptr< Type > &type, Term::Dir dir, const std::shared_ptr< ClockDomain > &domain)
Make a new port with some name, type and direction.
Definition: port.cc:22
cerata::vhdl
Contains everything related to the VHDL back-end.
Definition: architecture.cc:31