Fletchgen
The Fletcher Design Generator
src
fletchgen
top
sim_template.h
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// Copyright 2018-2019 Delft University of Technology
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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namespace
fletchgen::top {
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// TODO(johanpel): Insert this template through resource linking.
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static
char
sim_source[] =
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"-- Copyright 2018-2019 Delft University of Technology\n"
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"--\n"
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"-- Licensed under the Apache License, Version 2.0 (the \"License\");\n"
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"-- you may not use this file except in compliance with the License.\n"
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"-- You may obtain a copy of the License at\n"
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"--\n"
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"-- http://www.apache.org/licenses/LICENSE-2.0\n"
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"--\n"
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"-- Unless required by applicable law or agreed to in writing, software\n"
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"-- distributed under the License is distributed on an \"AS IS\" BASIS,\n"
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"-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n"
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"-- See the License for the specific language governing permissions and\n"
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"-- limitations under the License.\n"
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"\n"
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"library ieee;\n"
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"use ieee.std_logic_1164.all;\n"
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"use ieee.numeric_std.all;\n"
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"use ieee.std_logic_misc.all;\n"
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"\n"
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"library work;\n"
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"use work.Interconnect_pkg.all;\n"
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"use work.UtilStr_pkg.all;\n"
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"use work.UtilConv_pkg.all;\n"
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"\n"
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"entity SimTop_tc is\n"
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" generic (\n"
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" -- Accelerator properties\n"
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" INDEX_WIDTH : natural := 32;\n"
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" TAG_WIDTH : natural := 1;\n"
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"\n"
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" -- Host bus properties\n"
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" BUS_ADDR_WIDTH : natural := ${BUS_ADDR_WIDTH};\n"
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" BUS_DATA_WIDTH : natural := ${BUS_DATA_WIDTH};\n"
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" BUS_LEN_WIDTH : natural := ${BUS_LEN_WIDTH};\n"
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" BUS_BURST_MAX_LEN : natural := ${BUS_BURST_MAX_LEN};\n"
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" BUS_BURST_STEP_LEN : natural := ${BUS_BURST_STEP_LEN}\n"
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" );\n"
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"end SimTop_tc;\n"
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"\n"
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"architecture Behavorial of SimTop_tc is\n"
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"\n"
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" -----------------------------------------------------------------------------\n"
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" -- Default wrapper component.\n"
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" -----------------------------------------------------------------------------\n"
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" ${MANTLE_DECL}"
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" -----------------------------------------------------------------------------\n"
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"\n"
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" -- Fletcher defaults\n"
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" constant REG_CONTROL : natural := 0;\n"
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" constant REG_STATUS : natural := 1;\n"
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" constant REG_RETURN0 : natural := 2;\n"
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" constant REG_RETURN1 : natural := 3;\n"
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"\n"
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" constant CONTROL_CLEAR : std_logic_vector(31 downto 0) := X\"00000000\";\n"
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" constant CONTROL_START : std_logic_vector(31 downto 0) := X\"00000001\";\n"
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" constant CONTROL_STOP : std_logic_vector(31 downto 0) := X\"00000002\";\n"
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" constant CONTROL_RESET : std_logic_vector(31 downto 0) := X\"00000004\";\n"
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"\n"
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" constant STATUS_IDLE : std_logic_vector(31 downto 0) := X\"00000001\";\n"
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" constant STATUS_BUSY : std_logic_vector(31 downto 0) := X\"00000002\";\n"
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" constant STATUS_DONE : std_logic_vector(31 downto 0) := X\"00000004\";\n"
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"\n"
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" -- Sim signals\n"
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" signal clock_stop : boolean := false;\n"
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"\n"
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" -- Accelerator signals\n"
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" signal kcd_clk : std_logic;\n"
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" signal kcd_reset : std_logic;\n"
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"\n"
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" -- Fletcher bus signals\n"
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" signal bcd_clk : std_logic;\n"
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" signal bcd_reset : std_logic;\n"
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"\n"
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" -- External signals\n"
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"${EXTERNAL_SIG_DECL}"
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"\n"
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" -- MMIO signals\n"
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" signal mmio_awvalid : std_logic := '0';\n"
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" signal mmio_awready : std_logic := '0';\n"
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" signal mmio_awaddr : std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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" signal mmio_wvalid : std_logic := '0';\n"
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" signal mmio_wready : std_logic := '0';\n"
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" signal mmio_wdata : std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" signal mmio_wstrb : std_logic_vector(${MMIO_DATA_WIDTH}/8-1 downto 0);\n"
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" signal mmio_bvalid : std_logic := '0';\n"
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" signal mmio_bready : std_logic := '0';\n"
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" signal mmio_bresp : std_logic_vector(1 downto 0);\n"
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" signal mmio_arvalid : std_logic := '0';\n"
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" signal mmio_arready : std_logic := '0';\n"
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" signal mmio_araddr : std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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" signal mmio_rvalid : std_logic := '0';\n"
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" signal mmio_rready : std_logic := '0';\n"
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" signal mmio_rdata : std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" signal mmio_rresp : std_logic_vector(1 downto 0);\n"
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"\n"
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" -- Mmio signals to source in mmio procedures.\n"
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" type mmio_source_t is record\n"
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" awvalid : std_logic;\n"
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" awaddr : std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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" wvalid : std_logic;\n"
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" wdata : std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" wstrb : std_logic_vector(${MMIO_DATA_WIDTH}/8-1 downto 0);\n"
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" bready : std_logic;\n"
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"\n"
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" arvalid : std_logic;\n"
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" araddr : std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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" rready : std_logic;\n"
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" end record;\n"
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"\n"
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" -- Mmio signals to sink in mmio procedures\n"
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" type mmio_sink_t is record\n"
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" wready : std_logic;\n"
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"\n"
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" awready : std_logic;\n"
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"\n"
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" bvalid : std_logic;\n"
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" bresp : std_logic_vector(1 downto 0);\n"
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"\n"
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" arready : std_logic;\n"
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"\n"
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" rvalid : std_logic;\n"
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" rdata : std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" rresp : std_logic_vector(1 downto 0);\n"
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" end record;\n"
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"\n"
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" signal mmio_source : mmio_source_t;\n"
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" signal mmio_sink : mmio_sink_t;\n"
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"\n"
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" -- Memory interface signals\n"
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" signal bus_rreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" signal bus_rreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" signal bus_rreq_valid : std_logic;\n"
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" signal bus_rreq_ready : std_logic;\n"
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" signal bus_rdat_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" signal bus_rdat_last : std_logic;\n"
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" signal bus_rdat_valid : std_logic;\n"
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" signal bus_rdat_ready : std_logic;\n"
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" signal bus_wreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" signal bus_wreq_last : std_logic;\n"
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" signal bus_wreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" signal bus_wreq_valid : std_logic;\n"
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" signal bus_wreq_ready : std_logic;\n"
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" signal bus_wdat_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" signal bus_wdat_strobe : std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
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" signal bus_wdat_last : std_logic;\n"
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" signal bus_wdat_valid : std_logic;\n"
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" signal bus_wdat_ready : std_logic;\n"
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" signal bus_wrep_ok : std_logic;\n"
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" signal bus_wrep_valid : std_logic;\n"
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" signal bus_wrep_ready : std_logic;\n"
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"\n"
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" procedure mmio_write32 (constant idx : in natural;\n"
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" constant data : in std_logic_vector(31 downto 0);\n"
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" signal source : out mmio_source_t;\n"
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" signal sink : in mmio_sink_t;\n"
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" signal clk : in std_logic;\n"
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" signal reset : in std_logic)\n"
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" is\n"
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" begin\n"
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" -- Wait for reset\n"
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" loop\n"
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" exit when reset = '0';\n"
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" wait until rising_edge(clk);\n"
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" end loop;\n"
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" -- Address write channel\n"
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" source.awaddr <= slv(${MMIO_OFFSET} + (32/8)*idx, ${MMIO_ADDR_WIDTH});\n"
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" source.awvalid <= '1';\n"
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" loop\n"
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" wait until rising_edge(clk);\n"
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" exit when sink.awready = '1';\n"
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" end loop;\n"
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" source.awvalid <= '0';\n"
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" source.awaddr <= (others => 'U');\n"
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" -- Write channel\n"
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" source.wdata${MMIO_RW_DATA_RANGE} <= data;\n"
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" source.wstrb <= ${MMIO_STRB};\n"
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" source.wvalid <= '1';\n"
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" loop\n"
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" wait until rising_edge(clk);\n"
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" exit when sink.wready = '1';\n"
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" end loop;\n"
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" source.wvalid <= '0';\n"
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" source.wdata <= (others => 'U');\n"
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" source.wstrb <= (others => 'U');\n"
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" -- Write response channel.\n"
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" source.bready <= '1';\n"
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" loop\n"
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" wait until rising_edge(clk);\n"
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" exit when sink.bvalid = '1';\n"
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" end loop;\n"
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" source.bready <= '0';\n"
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" end procedure;\n"
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"\n"
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" procedure mmio_read32(constant idx : in natural;\n"
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" variable data : out std_logic_vector(31 downto 0);\n"
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" signal source : out mmio_source_t;\n"
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" signal sink : in mmio_sink_t;\n"
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" signal clk : in std_logic;\n"
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" signal reset : in std_logic)\n"
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" is\n"
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" begin\n"
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" -- Wait for reset\n"
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" loop\n"
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" exit when reset = '0';\n"
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" wait until rising_edge(clk);\n"
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" end loop;\n"
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" -- Address read channel\n"
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" source.araddr <= slv(${MMIO_OFFSET} + (32/8)*idx, ${MMIO_ADDR_WIDTH});\n"
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" source.arvalid <= '1';\n"
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" loop\n"
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" wait until rising_edge(clk);\n"
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" exit when sink.arready = '1';\n"
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" end loop;\n"
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" source.arvalid <= '0';\n"
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" source.araddr <= (others => 'U');\n"
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" -- Read channel\n"
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" loop\n"
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" source.rready <= '1';\n"
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" wait until rising_edge(clk);\n"
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" if sink.rvalid = '1' then\n"
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" data := sink.rdata${MMIO_RW_DATA_RANGE};\n"
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" exit;\n"
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" end if;\n"
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" end loop;\n"
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" source.rready <= '0';\n"
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" end procedure;\n"
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"\n"
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"\n"
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"begin\n"
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"\n"
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" -- Connect to records for easier readibility downstream.\n"
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" mmio_awvalid <= mmio_source.awvalid;\n"
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" mmio_awaddr <= mmio_source.awaddr;\n"
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" mmio_wvalid <= mmio_source.wvalid;\n"
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" mmio_wdata <= mmio_source.wdata;\n"
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" mmio_wstrb <= mmio_source.wstrb;\n"
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" mmio_bready <= mmio_source.bready;\n"
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" mmio_arvalid <= mmio_source.arvalid;\n"
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" mmio_araddr <= mmio_source.araddr;\n"
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" mmio_rready <= mmio_source.rready;\n"
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"\n"
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" mmio_sink.wready <= mmio_wready;\n"
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" mmio_sink.awready <= mmio_awready;\n"
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" mmio_sink.bvalid <= mmio_bvalid;\n"
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" mmio_sink.bresp <= mmio_bresp;\n"
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" mmio_sink.arready <= mmio_arready;\n"
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" mmio_sink.rvalid <= mmio_rvalid;\n"
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" mmio_sink.rdata <= mmio_rdata;\n"
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" mmio_sink.rresp <= mmio_rresp;\n"
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"\n"
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"\n"
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" -- Typical stimuli process:\n"
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" stimuli_proc : process is\n"
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" variable read_data : std_logic_vector(31 downto 0) := X\"DEADBEEF\";\n"
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" variable read_data_masked : std_logic_vector(31 downto 0);\n"
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" begin\n"
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" mmio_source.awvalid <= '0';\n"
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" mmio_source.wvalid <= '0';\n"
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" mmio_source.bready <= '0';\n"
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"\n"
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" mmio_source.arvalid <= '0';\n"
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" mmio_source.rready <= '0';\n"
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"\n"
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" wait until kcd_reset = '1' and bcd_reset = '1';\n"
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"\n"
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" -- 1. Reset the user core\n"
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" mmio_write32(REG_CONTROL, CONTROL_RESET, mmio_source, mmio_sink, bcd_clk, bcd_reset);\n"
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"\n"
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" -- 2. Write addresses of the arrow buffers in the SREC file.\n"
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"${SREC_BUFFER_ADDRESSES}\n"
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" -- 3. Write recordbatch bounds.\n"
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"${SREC_FIRSTLAST_INDICES}\n"
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" -- 4. Write any kernel-specific registers.\n"
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"${KERNEL_REGS_INIT}\n"
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" -- 5. Start the kernel.\n"
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"${PROFILE_START}"
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" mmio_write32(REG_CONTROL, CONTROL_START, mmio_source, mmio_sink, bcd_clk, bcd_reset);\n"
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"\n"
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" -- 6. Poll for completion\n"
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" loop\n"
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" -- Wait a bunch of cycles.\n"
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" for I in 0 to 8 loop\n"
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" wait until rising_edge(bcd_clk);\n"
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" end loop;\n"
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"\n"
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" -- Read the status register.\n"
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" mmio_read32(REG_STATUS, read_data, mmio_source, mmio_sink, bcd_clk, bcd_reset);\n"
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"\n"
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" -- Check if we're done.\n"
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" read_data_masked := read_data and STATUS_DONE;\n"
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" exit when read_data_masked = STATUS_DONE;\n"
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" end loop;\n"
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"\n"
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"${PROFILE_STOP}\n"
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" -- 7. Read return register.\n"
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" mmio_read32(REG_RETURN0, read_data, mmio_source, mmio_sink, bcd_clk, bcd_reset);\n"
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" println(\"Return register 0: \" & slvToHex(read_data));\n"
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" mmio_read32(REG_RETURN1, read_data, mmio_source, mmio_sink, bcd_clk, bcd_reset);\n"
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" println(\"Return register 1: \" & slvToHex(read_data));\n"
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"\n"
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" -- 8. Read profile registers.\n"
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"${PROFILE_READ}\n"
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" -- 9. Finish and stop simulation.\n"
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" report \"Stimuli done.\";\n"
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" clock_stop <= true;\n"
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"\n"
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" wait;\n"
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" end process;\n"
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"\n"
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" clk_proc: process is\n"
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" begin\n"
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" if not clock_stop then\n"
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" kcd_clk <= '1';\n"
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" bcd_clk <= '1';\n"
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" wait for 5 ns;\n"
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" kcd_clk <= '0';\n"
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" bcd_clk <= '0';\n"
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" wait for 5 ns;\n"
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" else\n"
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" wait;\n"
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" end if;\n"
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" end process;\n"
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"\n"
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" reset_proc: process is\n"
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" begin\n"
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" kcd_reset <= '1';\n"
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" bcd_reset <= '1';\n"
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" wait for 50 ns;\n"
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" wait until rising_edge(kcd_clk);\n"
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" kcd_reset <= '0';\n"
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" bcd_reset <= '0';\n"
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" wait;\n"
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" end process;\n"
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"\n"
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"${BUS_READ_SLAVE_MOCK}\n"
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"${BUS_WRITE_SLAVE_MOCK}\n"
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"\n"
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"\n"
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" -----------------------------------------------------------------------------\n"
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" -- Fletcher generated wrapper\n"
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" -----------------------------------------------------------------------------\n"
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" ${FLETCHER_WRAPPER_INST_NAME} : ${FLETCHER_WRAPPER_NAME}\n"
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" generic map (\n"
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" BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,\n"
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" BUS_DATA_WIDTH => BUS_DATA_WIDTH,\n"
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" BUS_BURST_STEP_LEN => BUS_BURST_STEP_LEN,\n"
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" BUS_BURST_MAX_LEN => BUS_ADDR_WIDTH,\n"
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" BUS_LEN_WIDTH => BUS_LEN_WIDTH,\n"
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" INDEX_WIDTH => INDEX_WIDTH,\n"
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" TAG_WIDTH => TAG_WIDTH\n"
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" )\n"
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" port map (\n"
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" kcd_clk => kcd_clk,\n"
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" kcd_reset => kcd_reset,\n"
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" bcd_clk => bcd_clk,\n"
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" bcd_reset => bcd_reset,\n"
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"${EXTERNAL_INST_MAP}\n"
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"${MST_RREQ_INSTANTIATE}\n"
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"${MST_WREQ_INSTANTIATE}\n"
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" mmio_awvalid => mmio_awvalid,\n"
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" mmio_awready => mmio_awready,\n"
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" mmio_awaddr => mmio_awaddr,\n"
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" mmio_wvalid => mmio_wvalid,\n"
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" mmio_wready => mmio_wready,\n"
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" mmio_wdata => mmio_wdata,\n"
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" mmio_wstrb => mmio_wstrb,\n"
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" mmio_bvalid => mmio_bvalid,\n"
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" mmio_bready => mmio_bready,\n"
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" mmio_bresp => mmio_bresp,\n"
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" mmio_arvalid => mmio_arvalid,\n"
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" mmio_arready => mmio_arready,\n"
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" mmio_araddr => mmio_araddr,\n"
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" mmio_rvalid => mmio_rvalid,\n"
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" mmio_rready => mmio_rready,\n"
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" mmio_rdata => mmio_rdata,\n"
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" mmio_rresp => mmio_rresp\n"
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" );\n"
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"\n"
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"end architecture;\n"
;
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}
// namespace fletchgen::top
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