Fletchgen
The Fletcher Design Generator
src
fletchgen
top
axi_template.h
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// Copyright 2018-2019 Delft University of Technology
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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namespace
fletchgen::top {
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// TODO(johanpel): Insert this template through resource linking.
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static
char
axi_source[] =
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"-- Copyright 2018-2019 Delft University of Technology\n"
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"--\n"
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"-- Licensed under the Apache License, Version 2.0 (the \"License\");\n"
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"-- you may not use this file except in compliance with the License.\n"
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"-- You may obtain a copy of the License at\n"
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"--\n"
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"-- http://www.apache.org/licenses/LICENSE-2.0\n"
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"--\n"
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"-- Unless required by applicable law or agreed to in writing, software\n"
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"-- distributed under the License is distributed on an \"AS IS\" BASIS,\n"
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"-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n"
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"-- See the License for the specific language governing permissions and\n"
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"-- limitations under the License.\n"
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"\n"
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"library ieee;\n"
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"use ieee.std_logic_1164.all;\n"
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"use ieee.numeric_std.all;\n"
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"use ieee.std_logic_misc.all;\n"
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"\n"
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"library work;\n"
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"use work.Axi_pkg.all;\n"
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"use work.UtilInt_pkg.all;\n"
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"use work.UtilConv_pkg.all;\n"
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"use work.UtilMisc_pkg.all;\n"
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"\n"
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"-------------------------------------------------------------------------------\n"
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"-- AXI4 compatible top level for Fletcher generated accelerators.\n"
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"-------------------------------------------------------------------------------\n"
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"-- Requires an AXI4 port to host memory.\n"
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"-- Requires an AXI4-lite port from host for MMIO.\n"
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"-------------------------------------------------------------------------------\n"
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"entity AxiTop is\n"
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" generic (\n"
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" -- Accelerator properties\n"
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" INDEX_WIDTH : natural := 32;\n"
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" REG_WIDTH : natural := 32;\n"
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" TAG_WIDTH : natural := 1;\n"
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" -- AXI4 (full) bus properties for memory access.\n"
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" BUS_ADDR_WIDTH : natural := ${BUS_ADDR_WIDTH};\n"
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" BUS_DATA_WIDTH : natural := ${BUS_DATA_WIDTH};\n"
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" BUS_LEN_WIDTH : natural := ${BUS_LEN_WIDTH};\n"
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" BUS_BURST_MAX_LEN : natural := ${BUS_BURST_MAX_LEN};\n"
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" BUS_BURST_STEP_LEN : natural := ${BUS_BURST_STEP_LEN}\n"
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" );\n"
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"\n"
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" port (\n"
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" -- Kernel clock domain.\n"
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" kcd_clk : in std_logic;\n"
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" kcd_reset : in std_logic;\n"
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" \n"
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" -- Bus clock domain.\n"
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" bcd_clk : in std_logic;\n"
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" bcd_reset : in std_logic;\n"
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"\n"
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" ---------------------------------------------------------------------------\n"
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" -- External signals\n"
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" ---------------------------------------------------------------------------\n"
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"${EXTERNAL_PORT_DECL}\n"
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" ---------------------------------------------------------------------------\n"
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" -- AXI4 master as Host Memory Interface\n"
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" ---------------------------------------------------------------------------\n"
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" -- Read address channel\n"
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" m_axi_araddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" m_axi_arlen : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" m_axi_arvalid : out std_logic := '0';\n"
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" m_axi_arready : in std_logic;\n"
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" m_axi_arsize : out std_logic_vector(2 downto 0);\n"
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"\n"
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" -- Read data channel\n"
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" m_axi_rdata : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" m_axi_rresp : in std_logic_vector(1 downto 0);\n"
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" m_axi_rlast : in std_logic;\n"
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" m_axi_rvalid : in std_logic;\n"
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" m_axi_rready : out std_logic := '0';\n"
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"\n"
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" -- Write address channel\n"
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" m_axi_awvalid : out std_logic := '0';\n"
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" m_axi_awready : in std_logic;\n"
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" m_axi_awaddr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" m_axi_awlen : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" m_axi_awsize : out std_logic_vector(2 downto 0);\n"
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" m_axi_awuser : out std_logic_vector(0 downto 0);\n"
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"\n"
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" -- Write data channel\n"
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" m_axi_wvalid : out std_logic := '0';\n"
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" m_axi_wready : in std_logic;\n"
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" m_axi_wdata : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" m_axi_wlast : out std_logic;\n"
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" m_axi_wstrb : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
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"\n"
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" -- Write response channel\n"
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" m_axi_bvalid : in std_logic;\n"
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" m_axi_bready : out std_logic;\n"
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" m_axi_bresp : in std_logic_vector(1 downto 0);\n"
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" ---------------------------------------------------------------------------\n"
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" -- AXI4-lite Slave as MMIO interface\n"
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" ---------------------------------------------------------------------------\n"
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" -- Write address channel\n"
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" s_axi_awvalid : in std_logic;\n"
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" s_axi_awready : out std_logic;\n"
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" s_axi_awaddr : in std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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"\n"
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" -- Write data channel\n"
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" s_axi_wvalid : in std_logic;\n"
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" s_axi_wready : out std_logic;\n"
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" s_axi_wdata : in std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" s_axi_wstrb : in std_logic_vector((${MMIO_DATA_WIDTH}/8)-1 downto 0);\n"
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"\n"
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" -- Write response channel\n"
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" s_axi_bvalid : out std_logic;\n"
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" s_axi_bready : in std_logic;\n"
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" s_axi_bresp : out std_logic_vector(1 downto 0);\n"
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"\n"
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" -- Read address channel\n"
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" s_axi_arvalid : in std_logic;\n"
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" s_axi_arready : out std_logic;\n"
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" s_axi_araddr : in std_logic_vector(${MMIO_ADDR_WIDTH}-1 downto 0);\n"
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"\n"
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" -- Read data channel\n"
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" s_axi_rvalid : out std_logic;\n"
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" s_axi_rready : in std_logic;\n"
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" s_axi_rdata : out std_logic_vector(${MMIO_DATA_WIDTH}-1 downto 0);\n"
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" s_axi_rresp : out std_logic_vector(1 downto 0)\n"
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" );\n"
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"end AxiTop;\n"
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"\n"
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"architecture Behavorial of AxiTop is\n"
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"\n"
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" -----------------------------------------------------------------------------\n"
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" -- Generated top-level wrapper component.\n"
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" -----------------------------------------------------------------------------\n"
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" ${MANTLE_DECL}"
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" -----------------------------------------------------------------------------\n"
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" -- Internal signals. \n"
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" \n"
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" -- Active low reset for bus clock domain\n"
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" signal bcd_reset_n : std_logic;\n"
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" \n"
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" -- Bus signals to convert to AXI.\n"
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" signal rd_mst_rreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" signal rd_mst_rreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" signal rd_mst_rreq_valid : std_logic;\n"
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" signal rd_mst_rreq_ready : std_logic;\n"
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" signal rd_mst_rdat_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" signal rd_mst_rdat_last : std_logic;\n"
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" signal rd_mst_rdat_valid : std_logic;\n"
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" signal rd_mst_rdat_ready : std_logic;\n"
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" signal wr_mst_wreq_valid : std_logic;\n"
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" signal wr_mst_wreq_ready : std_logic;\n"
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" signal wr_mst_wreq_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);\n"
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" signal wr_mst_wreq_len : std_logic_vector(BUS_LEN_WIDTH-1 downto 0);\n"
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" signal wr_mst_wreq_last : std_logic;\n"
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" signal wr_mst_wdat_valid : std_logic;\n"
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" signal wr_mst_wdat_ready : std_logic;\n"
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" signal wr_mst_wdat_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);\n"
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" signal wr_mst_wdat_strobe : std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);\n"
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" signal wr_mst_wdat_last : std_logic;\n"
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" signal wr_mst_wrep_valid : std_logic;\n"
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" signal wr_mst_wrep_ready : std_logic;\n"
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" signal wr_mst_wrep_ok : std_logic;\n"
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"\n"
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"begin\n"
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"\n"
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" -- Active low reset\n"
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" bcd_reset_n <= not bcd_reset;\n"
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"\n"
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" -----------------------------------------------------------------------------\n"
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" -- Fletcher generated wrapper\n"
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" -----------------------------------------------------------------------------\n"
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" ${FLETCHER_WRAPPER_INST_NAME} : ${FLETCHER_WRAPPER_NAME}\n"
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" generic map (\n"
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" BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,\n"
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" BUS_DATA_WIDTH => BUS_DATA_WIDTH,\n"
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" BUS_BURST_STEP_LEN => BUS_BURST_STEP_LEN,\n"
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" BUS_BURST_MAX_LEN => BUS_BURST_MAX_LEN,\n"
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" BUS_LEN_WIDTH => BUS_LEN_WIDTH,\n"
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" INDEX_WIDTH => INDEX_WIDTH,\n"
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" TAG_WIDTH => TAG_WIDTH\n"
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" )\n"
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" port map (\n"
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" kcd_clk => kcd_clk,\n"
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" kcd_reset => kcd_reset,\n"
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" bcd_clk => bcd_clk,\n"
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" bcd_reset => bcd_reset,\n"
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"${EXTERNAL_INST_MAP}\n"
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"${MST_RREQ_INSTANTIATE}\n"
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"${MST_WREQ_INSTANTIATE}\n"
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" mmio_awvalid => s_axi_awvalid,\n"
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" mmio_awready => s_axi_awready,\n"
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" mmio_awaddr => s_axi_awaddr,\n"
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" mmio_wvalid => s_axi_wvalid,\n"
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" mmio_wready => s_axi_wready,\n"
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" mmio_wdata => s_axi_wdata,\n"
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" mmio_wstrb => s_axi_wstrb,\n"
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" mmio_bvalid => s_axi_bvalid,\n"
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" mmio_bready => s_axi_bready,\n"
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" mmio_bresp => s_axi_bresp,\n"
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" mmio_arvalid => s_axi_arvalid,\n"
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" mmio_arready => s_axi_arready,\n"
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" mmio_araddr => s_axi_araddr,\n"
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" mmio_rvalid => s_axi_rvalid,\n"
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" mmio_rready => s_axi_rready,\n"
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" mmio_rdata => s_axi_rdata,\n"
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" mmio_rresp => s_axi_rresp\n"
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" );\n"
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"\n"
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"${AXI_READ_CONVERTER}\n"
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"${AXI_WRITE_CONVERTER}\n"
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"\n"
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"end architecture;"
;
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}
// namespace fletchgen::top
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