Tydi in VHDL

While there is no direct, currently maintained, implementation of Tydi interfaces in VHDL, there are some previous tools that are relevant for creating an implementation in VHDL.

The TIL -> VHDL tool allows generating VHDL boilerplate code for Tydi interfaces from an interface description in the Tidy Intermediate Language (TIL). This can be used in conjunction with V1 of Tydi-lang to write interfaces in Tydi-lang dialect instead.